Anti-CML monoclonal antibody, clone 7D8

SARS-CoV-2 is the viral agent responsible for the pandemic that in the first months of 2020 caused about 400,000 deaths. Among compounds proposed to fight the SARS-CoV-2-related disease (COVID-19), tyrosine kinase inhibitors (TKIs), already effective in Philadelphia-positive acute lymphoblastic leukemia (Ph+ ALL) and chronic myeloid leukemia (CML), have been proposed on the basis of their antiviral action already demonstrated against SARS-CoV-1. Very few cases of COVID-19 have been reported in Ph+ ALL and in CML Italian cohorts; authors suggested that this low rate of infections might depend on the use of TKIs, but the biological causes of this phenomenon remain unknown. In this study, the CML model was used to test if TKIs would sustain or not the viral replication and if they could damage patient immunity. Firstly, the infection and replication rate of torquetenovirus (TTV), whose load is inversely proportional to the host immunological control, have been measured in CML patients receiving nilotinib. A very low percentage of subjects were infected at baseline, and TTV did not replicate or at least showed a low replication rate during the follow-up, with a mean load comparable to the measured one in healthy subjects. Then, after gene expression profiling experiments, we found that several "antiviral" genes, such asCD28andIFN gamma, were upregulated, while genes with "proviral" action, such asARG-1, CEACAM1, andFUT4, were less expressed during treatment with imatinib, thus demonstrating that TKIs are not detrimental from the immunological point of view. To sum up, our data could offer some biological explanations to the low COVID-19 occurrence in Ph+ ALL and CML patients and sustain the use of TKIs in COVID-19, as already proposed by several international ongoing studies.

In this letter, a novel high-speed widely tunable voltage-controlled current mode logic (CML) delay cell is implemented in a 65-nm CMOS technology. Variation in the delay of the proposed delay cell is based on the hysteresis control of the output switching threshold by altering the tail current of the CML buffer. The simulation for a single stage cell shows a delay variation of at least 11% in the input clock period at 12.5-GHz clock frequency. While in measurement, the delay line with three stages of the proposed cells shows more than a 38-ps delay variation with an output rms jitter of 1.67 ps for the 9.82-GHz input clock frequency. At this frequency with the highest delay variation, along with additional buffers and delay controllers, the delay line consumes 7.6 mW of power with 1.2-V core supply. The delay line consumes the silicon area of 0.0285 mm(2) in the 65-nm technology node.