Anti-RTP2 polyclonal antibody

Cobalt salicide-induced static random access-memory (SRAM) leakage in 90-nm technology is investigated in this paper. We found that the junction leakages are the origins of abnormal SRAM leakage, leading to a high direct-drain quiescent current and low function yield at wafer level. Cobalt salicide penetration at active edges is a dominant path for the junction leakage current. Both junction-area-intensive and active-edgeintensive test structures are employed to characterize the junction leakage. The SRAM function failure sites are carefully examined using conducting atomic force microscope and transmission electron microscope techniques. A full-factorial design of experiment (DOE) is implemented to systematically study the influences of Co thickness and temperatures of RTP1 and RTP2 on the junction leakage characteristics. Within the DOE window, it is found that both junction area and junction edge leakages increase with the Co thickness. The RTP1 temperature is critical in controlling Co salicide penetration at the active edge, while the RTP2 temperature is the main factor that affects the junction area leakage. SRAM leakage can be minimized by optimizing the salicide process scheme.

The effect of some key variables such as rapid thermal processing (RTP) temperature, substrate cleaning method and capping layers, on cobalt silicide formation has been investigated. The in-situ RF sputter etch is found to give a post RTP2 R-sh that is equivalent to a wet cleaned wafer. The temperature transformation curve of cobalt films, analyzed with R-sh data and XRD, reveal the formation of Co2Si-CoSi-CoSi2 phases in that order. The transformation curves of TiN capped films match those of blanket cobalt but the Ti capped films show the CoSi phase to be stable over a broader temperature range. There is no effect of dopants on the final cobalt disilicide R-sh values for either the single or polycrystalline substrates. Controlled oxygen leak studies in the RTP ambient reveal that the R-sh after RTP1 is degraded if a capping layer is not present. Electrical test results confirm the need for capping layers. This is indicated by lower R-sh and R-c values on both n+ and p+ junctions and poly structures. Furthermore the electrical results are comparable for Ti and TiN layers used as the cap films although the R-sh/R-c values are in general lower for the TiN capped films. Poly gate length vs R-sh plots show the extendibility of the capped cobalt silicide process to the 0.18um node.