Enhanced holoentropy-based encoding via whale optimization for highly efficient video coding
VISUAL COMPUTER
Authors: Munagala, Venkatesh; Kodati, Satya Prasad
Abstract
High-efficiency video coding (HEVC), a video compression method is considered as the most capable descendant of the extensively deployed advanced VC (AVC). Compared with AVC, HEVC provides about twice the data compression ratio at the similar video quality level or considerably enhanced video quality at an equal bit rate. This paper proposes a novel enhanced holoentropy model for proficient systems for distributed VC (DVC). HEVC standard is considered as an archetypal system. The main contribution of this paper is the accomplishment of the encoding process in the HEVC system by enhanced holoentropy, which is linked with the proposed weighting tansig function. It necessitates considerable development when handling video sequences with high resolution. The pixel deviations under altering frames are grouped based on interest, and the outliers are eliminated with the aid of an enhanced entropy standard known as enhanced holoentropy. Here, the weight of tansig function is optimally tuned by whale optimization algorithm. To next of implementation, the suggested encoding scheme is compared with the conventional schemes concerning the number of compressed bits and computational time. By carrying out the encoding process, it reduces the video size with perceptually improved video quality or PSNR.
Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things
SENSORS
Authors: Rashid, Muhammad; Baloch, Naveed Khan; Shafique, Muhammad Akmal; Hussain, Fawad; Saleem, Shahroon; Zikria, Yousaf Bin; Yu, Heejung
Abstract
Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers.