Anti-DCX monoclonal antibody, clone 5B4

Endogenous neurogenesis can arise from a variety of physiological stimuli including exercise, learning, or "enriched environment" as well as pathological conditions such as ischemia, epilepsy or cortical spreading depression. Whether all these conditions use a common trigger to set off endogenous neurogenesis is yet unclear. We hypothesized that cortical spreading depression (CSD) induces neurogenesis in the cerebral cortex and dentate gyrus after cerebral venous ischemia. Forty-two Wistar rats alternatively underwent sham operation (Sham), induction of ten CSDs or venous ischemia provoked via occlusion of two adjacent superficial cortical vein followed by ten induced CSDs (CSD + 2-VO). As an additional control, 15 naive rats received no intervention except 5-bromo-2'-deoxyuridine (BrdU) treatment for 7 days. Sagittal brain slices (40 mu m thick) were co-stained for BrdU and doublecortin (DCX; new immature neuronal cells) on day 9 or NeuN (new mature neuronal cells) on day 28. On day 9 after sham operation, cell proliferation and neurogenesis occurred in the cortex in rats. The sole induction of CSD had no effect. But on days 9 and 28, more proliferating cells and newly formed neurons in the ipsilateral cortex were observed in rats subjected to CSD + 2VO than in rats subjected to sham operation. On days 9 and 28, cell proliferation and neurogenesis in the ipsilateral dentate gyrus was increased in sham-operated rats than in naive rats. Our data supports the hypothesis that induced cortical neurogenesis after CSD + 2-VO is a direct effect of ischemia, rather than of CSD alone.

Drain-source voltage-sensed synchronous rectification (SR) is a technique used that can be used to reduce the secondary-side diode conduction loss of an LLC converter. In drain-source SR, an early SR-switch turn off issue is observed due to parasitics present in the power path of the rectifier drain-source sensing loop. In rectifiers with parallel switches, sequential parallel switching (SPS) can be utilized to increase the drain-source signal integrity near turn off. In rectifiers where a single SR switch is used, multilevel turn-off can be used to reduce the parasitic effects and allow for a more accurate SR turn-off. By reducing the gate voltage prior to SR turn-off, the drain-source voltage signal near the turn-off moment can be boosted to minimize the parasitic drain-source phase shift effect, extending the total SR conduction time. Multi-level turn off also reduces the amount of turn-off edge jitter experienced, which can start an internal unstable resonance at light-load conditions. By increasing the SR conduction time, multilevel turn-off can decrease body or antiparallel diode conduction loss in the LLC rectifier. This results in a net increase in total converter efficiency, despite a small increase in the SR FET channel conduction loss from the prolonged channel conduction time. A discrete three-level multilevel gate driver is built to test this concept, simulations are in the process of being run, and verification with silicon carbide SR FETs is performed on a 2.5kW LLC-DCX module.